EC1401 VLSI DESIGN 3 0 0 100
AIM
To introduce the technology, design concepts and testing of Very Large Scale Integrated Circuits.
OBJECTIVES
• To learn the basic CMOS circuits.
• To learn the CMOS process technology.
• To learn techniques of chip design using programmable devices.
• To learn the concepts of designing VLSI subsystems.
• To learn the concepts of modeling a digital system using Hardware Description Language.
UNIT I CMOS TECHNOLOGY 9
An overview of Silicon semiconductor technology, Basic CMOS technology : nwell,
P well, Twin tub and SOI Process. Interconnects, circuit elements: Resistors, capacitors, Electrically alterable ROMs, bipolar transistors, Latch up and prevention.
Layout design rules, physical design: basic concepts, CAD tool sets, physical design of logic gates: Inverter, NAND, NOR, Design Hierarchies.
UNIT II MOS TRANSISTOR THEORY 9
NMOS, PMOS Enhancement transistor, Threshold voltage, Body effect, MOS DC equations, channel length modulation, Mobility variation, MOS models, small signal AC characteristics, complementary CMOS inverter DC characteristics, Noise Margin, Rise time, fall time, power dissipation, transmission gate, tristate inverter.
UNIT III SPECIFICATION USING VERILOG HDL 9
Basic Concepts: VLSI Design flow, identifiers, gate primitives, value set, ports, gate delays, structural gate level and switch level modeling, Design hierarchies, Behavioral and RTL modeling: Operators, timing controls, Procedural assignments conditional statements, Data flow modeling and RTL.
Structural gate level description of decoder, equality detector, comparator, priority encoder, D-latch, D-ff, half adder, Full adder, Ripple Carry adder.
UNIT IV CMOS CHIP DESIGN 9
Logic design with CMOS: MOSFETS as switches, Basic logic gates in CMOS, Complex logic gates, Transmission gates: Muxes and latches, CMOS chip design options: Full custom ASICs, Std. Cell based ASICs, Gate Array based ASICs Channelled, Channelless and structured GA, Programmable logic structures; 22V10, Programming of PALs, Programmable Interconnect, Reprogrammable GA: Xilinx programmable GA, ASIC design flow.
UNIT V CMOS TESTING 9
Need for testing, manufacturing test principles, Design strategies for test, Chip level and system level test techniques.
TOTAL : 45
TEXT BOOKS
1. Weste & Eshraghian: Principles of CMOS VLSI design (2/e) Addison Wesley, 1993 for UNIT I through UNIT IV.
2. Samir Palnitkar; Verilog HDL - Guide to Digital design and synthesis, III edition, Pearson Education, 2003 for UNIT V
REFERENCES
1. M.J.S.Smith : Application Specific integrated circuits, Pearson Education, 1997.
2. Wayne Wolf, Modern VLSI Design, Pearson Education 2003.
3. Bob Zeidmin ; Introduction to verilog, Prentice Hall, 1999
4. J . Bhaskar : Verilog HDL Primer, BSP, 2002.
5. E. Fabricious , Introduction to VLSI design, McGraw-Hill 1990.
6. C. Roth, Digital Systems Design Using VHDL, Thomson Learning, 2000.
AIM
To introduce the technology, design concepts and testing of Very Large Scale Integrated Circuits.
OBJECTIVES
• To learn the basic CMOS circuits.
• To learn the CMOS process technology.
• To learn techniques of chip design using programmable devices.
• To learn the concepts of designing VLSI subsystems.
• To learn the concepts of modeling a digital system using Hardware Description Language.
UNIT I CMOS TECHNOLOGY 9
An overview of Silicon semiconductor technology, Basic CMOS technology : nwell,
P well, Twin tub and SOI Process. Interconnects, circuit elements: Resistors, capacitors, Electrically alterable ROMs, bipolar transistors, Latch up and prevention.
Layout design rules, physical design: basic concepts, CAD tool sets, physical design of logic gates: Inverter, NAND, NOR, Design Hierarchies.
UNIT II MOS TRANSISTOR THEORY 9
NMOS, PMOS Enhancement transistor, Threshold voltage, Body effect, MOS DC equations, channel length modulation, Mobility variation, MOS models, small signal AC characteristics, complementary CMOS inverter DC characteristics, Noise Margin, Rise time, fall time, power dissipation, transmission gate, tristate inverter.
UNIT III SPECIFICATION USING VERILOG HDL 9
Basic Concepts: VLSI Design flow, identifiers, gate primitives, value set, ports, gate delays, structural gate level and switch level modeling, Design hierarchies, Behavioral and RTL modeling: Operators, timing controls, Procedural assignments conditional statements, Data flow modeling and RTL.
Structural gate level description of decoder, equality detector, comparator, priority encoder, D-latch, D-ff, half adder, Full adder, Ripple Carry adder.
UNIT IV CMOS CHIP DESIGN 9
Logic design with CMOS: MOSFETS as switches, Basic logic gates in CMOS, Complex logic gates, Transmission gates: Muxes and latches, CMOS chip design options: Full custom ASICs, Std. Cell based ASICs, Gate Array based ASICs Channelled, Channelless and structured GA, Programmable logic structures; 22V10, Programming of PALs, Programmable Interconnect, Reprogrammable GA: Xilinx programmable GA, ASIC design flow.
UNIT V CMOS TESTING 9
Need for testing, manufacturing test principles, Design strategies for test, Chip level and system level test techniques.
TOTAL : 45
TEXT BOOKS
1. Weste & Eshraghian: Principles of CMOS VLSI design (2/e) Addison Wesley, 1993 for UNIT I through UNIT IV.
2. Samir Palnitkar; Verilog HDL - Guide to Digital design and synthesis, III edition, Pearson Education, 2003 for UNIT V
REFERENCES
1. M.J.S.Smith : Application Specific integrated circuits, Pearson Education, 1997.
2. Wayne Wolf, Modern VLSI Design, Pearson Education 2003.
3. Bob Zeidmin ; Introduction to verilog, Prentice Hall, 1999
4. J . Bhaskar : Verilog HDL Primer, BSP, 2002.
5. E. Fabricious , Introduction to VLSI design, McGraw-Hill 1990.
6. C. Roth, Digital Systems Design Using VHDL, Thomson Learning, 2000.
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